1. Field of the Invention
This invention relates to integrated circuit semiconductor memories, and particularly to an improved semiconductor memory device for use in serial scan applications.
2. Description of the Prior Art
Certain problems have been encountered with the use of semiconductor memories in serial scan applications, i.e. applications in which memory data is serially read to a utilization device. In particular, the restrictions on time available for memory access during the scanning operation causes overall system performance to suffer.
An example of the memory access problems that are encountered in serial scan applications can be seen in the use of semiconductor memories in video display systems. The preferred embodiment of the present invention relates in general to such applications, and in particular to display memory applications for bit-mapped graphics processor systems.
In general a graphics processor is an integrated circuit device which causes graphics symbols to be displayed on a video screen in response to a system user's input on a standard keyboard terminal. In a graphics processor video display system the graphics processor is linked to a video display memory system.
In a video display memory system, the display memory is often larger than the screen memory (that portion displayed on a screen at any given time). The screen memory may be moved horizontally or vertically relative to the display memory. This process is called scrolling. Furthermore, a non-contiguous portion of the display memory contents may be moved to the screen memory at an arbitrary location. This process is known as windowing.
In a video display system as described above, the data contained in the display memory must be continually updated within a certain period of time available for such updating.
The screen used in a typical video display system is a cathode ray tube (CRT). The information displayed at any given time on a CRT screen must be refreshed at a standard screen rate.
The operation of causing graphics symbols to be displayed on a video screen therefore involves two separate sub-operations--the processing of graphics information in response to user input, and the displaying of graphics symbols on a video screen. Hence, the graphics processor is required to perform two continual functions--updating the display memory contents and refreshing the CRT screen. To perform both functions, the graphics processor must subtract from the time available for updating the display memory to accomodate the screen refresh. This shared funtionality causes system performance (e.g. system speed, windowing and scrolling functions) to suffer significantly.
A major improvement in system performance can be made if the update and screen refresh functions are separated. This separation can be accomplished by devising a video dynamic random access memory (Video DRAM) system which includes an on-chip shift register. The shift register operates to accept a large number of parallel bits (e.g. 256 or 512) in one transfer cycle of perhaps 300 nanoseconds and then shifts data out in response to a high-speed video clock. This data is shifted out through a separate input and output independent of the random access memory's (RAM's) input and output, and thus, for all practical purposes the update and screen refresh functions are independent.
Video display memory systems have been developed which combine a DRAM with an on-board shift register. Such structures eliminate the bandwidth contention problem outlined above. However, current designs of such structures provide slow memory access (relative to the present invention) and coarse granularity of video display. Furthermore, scrolling can only be done on certain picture element (pixel) boundaries which are fixed as a function of the structure of the shift register employed in the system. Such designs provide only non-smooth scrolling with an erratic movement which is quite visible on a display screen. This form of "hard" scroll makes it difficult to scan rapidly through a document since the jumpy movement of the text cannot be followed by the eye.
Current designs also restrict the windowing process to the movement of data on fixed boundaries of bit positions within the display memory array. Such designs cannot provide smooth display screen panning of windowed data, due to the inherent restrictions on the windowing process. The inferior windowing and scrolling characteristic of such designs pose serious performance problems for video display graphics processor systems.